Intellectual Olympiad in Fundamentals of Microprocessor Technology - 2026 ongoing

Subject: Fundamentals of Microprocessor Technology
Level: XII
Category: student
Quiz questions: in English
Example question: A cache-coherent multiprocessor uses the MESI protocol. Core P1 holds a cache line in the Modified state, and core P2 issues a read request for that line. Which transition must occur at P1 before P2 can receive the current data? P1 changes the line to Shared and supplies or writes back the data, P1 retains Modified state and P2 receives stale memory data, P1 invalidates the line without supplying its data, P1 changes the line directly to Exclusive without communication